(a) Field of the Invention
The present invention relates to semiconductor devices, and more particularly it pertains to semiconductor devices such as modified IIL-type logic device and memory device having improved gate structures.
(b) Description of the Prior Art
Static induction transistors (SIT's) have been proposed first by the present inventor, and they actually have been put into use in some electronics fields, e.g. amplifier circuits, integrated logic devices, semiconductor memories and so forth. The SIT, as is well known, has many advantages over conventional bipolar and unipolar transistors in such aspects as high operating speed, high transconductance, low power dissipation, simple manufacturing process, high density integration and so on.
Those merits of the SIT can be effectively applied in integrated semiconductor devices such modified IIL-type logic devices as those disclosed in Japanese patent application No. 50-146588 (corresponding U.S. patent application No. 748,292 filed on Dec. 7, 1976) and Japanese patent application No. 51-92467 (corresponding U.S. patent application No. 819,343 filed on July 27, 1977). Such modified IIL-type logic devices have a basic arrangement as shown in FIGS. 1A and 1B.
FIG. 1A is a partially broken-away top plan view of these known IIL-type logic devices, mentioned above and FIG. 1B is a vertical sectional view taken along the line 1B-1B' in FIG. 1A. As shown, the device includes a heavily doped n.sup.+ type semiconductor substrate 11 and a lightly doped n.sup.- type semiconductor layer 12 deposited on the n.sup.+ type substrate 11. In this n.sup.- type semiconductor layer 12, there are formed heavily doped p.sup.+ type regions 14 and 50. The p+ type region 14 surrounds two separate portions of the n.sup.- type layer 12, thereby defining two separate current channels of an SIT as will be explained later in further detail. In the upper portions of those two current channel portions are formed heavily doped n.sup.+ type regions 13 which are operative as the drain (or source) regions of the SIT. On top of the respective n.sup.+, p.sup.+ and p.sup.+ regions 13, 14 and 50, there are deposited ohmic contact electrodes 23, 24 and 60. And also, another ohmic contact electrode 21 is formed at the bottom surface of the n.sup.+ type substrate 11. Reference numeral 16 represents a passivation film layer.
The above-mentioned device may be represented in an equivalent circuit in FIG. 1C, wherein an SIT Q.sub.1 with two drains, a source and a gate, and a bipolar transistor Q.sub.2 with a base, a collector and an emitter are shown. The SIT Q.sub.1 will be referred to as a driver or inverter transistor, whereas the bipolar transistor Q.sub.2 will be referred to as an injector or load transistor. The collector of the injector transistor Q.sub.2 is merged in and connected to the gate of the driver, transistor Q.sub.1 as will be described below in further detail.
The correlationship between FIG. 1C and FIGS. 1A and 1B is as follows. The injector is constituted by the region 50 (serving as the emitter region), the region 14 (serving as the collector region) and a portion of the layer located between the regions 14 and 50 (serving as the base region). The driver, i.e. a two-channel SIT, is formed by: the substrate 11 (serving here as the source region); the region 14 (serving as the gate region merged with the collector region); the region 13 (serving as the drain region); and those portions of the layer 12 defined by the gate region (which serve as the current channel regions).
With the simple structure described above, there has been obtained a modified IIL-type logic device which provides a power-delay product minimized to as low as 0.002 pJ at a low current operation condition, and a minimum propagation delay time of 13.8 nano-seconds or less at a power dissipation of 230 micro-watts. Furthermore, with some additional modifications such as those disclosed in Japanese patent application Nos. 51-143698 and 51-147253, there has been easily materialized a specimen of such IIL-type logic device whose minimum delay time is as small as a few nano-seconds or less.
In such modified IIL-type logic device, the limitation of the operating speed is caused mainly by a time delay for charging up the gate capacitance of the driver SIT and by a time delay due to minority carrier storage effect in the driver SIT. This will hereunder be explained in further detail. In order to achieve quick turning-on of the driver SIT, it is necessary for the gate potential to rapidly rise up to a certain voltage (typically 0.4-0.8 volt) with respect to the source so as to turn the current channel to be rendered conductive. As the driver SIT has a capacitance at the gate, the driver SIT is inherently accompanied by a time delay for driving, i.e. charging the gate capacitance thereof. This gate capacitance of the SIT is significantly small, but it serves to limit the maximum operation speed. On the other hand, when the driver SIT is in the conductive state, a certain amount of minority carriers are being injected from the forward-biased gate into the current channel. The injected minority carriers will develop an electric field which acts to attract majority carriers from the source into the current channel. This action of the injected minority carriers is considered to be effective for the SIT to supply a sufficient magnitude of drain current, even if the drain is held at a relatively low potential (typically 0.1-0.2 volt) with respect to the source. However, the minority carriers in the current channel will bring about an adverse storage effect in turning the SIT off, leading to a delayed turn-off action of this SIT.
On the other hand, semiconductor memory devices are developed to an extent that one transistor forms one memory cell. In such a structure, a memory cell is formed with a source region for supplying and retrieving charge carriers, a storage region for storing charge carriers and a channel region located between said two regions for controlling the flow of charge carriers therebetween under the control of a gate region. Among such memory cells, there are those types such as the so-called MOS FET type and the charge-coupled device type. However, memory cells of these two types occupy a rather large area in the surface of a semiconductor memory device.
Furthermore, charge carriers are transported mainly by the surface mobility in such devices. However, the bulk mobility in a semiconductor body is usually higher than the surface mobility due to various surface conditions such as trapping levels.
With respect to FET's, there have been developed a few which are provided with a plurality of gate electrodes for modifying their current-voltage characteristics. Among these latter FET's, TECNETRON and ARCATRON, for example, are known. These FET's are provided with a plurality of gate electrodes for controlling depletion layer in a channel region located between a source region and a drain region. However, these FET's exhibit mere conventional current-voltage characteristics, namely saturating pentode-like characteristics. Moreover, ARCATRON have a planar type structure of an FET with a small first gate region and a large second gate region for controlling the channel region, occupies a considerably large area in the surface of a semiconductor body. Therefore, when it is used in a memory device, a high packing density can not be realized.
Thus, ARCATRONS and TECNETRONS can not afford a semiconductor device of a high-speed operation and a high packing density.
While, a static induction transistor or a punchthrough type bipolar transistor which is employed in the present invention is such transistor which exhibits nonsaturating triode-like characteristics thereby enhancing a high speed operation with a large current gain. Also an static induction transistor having a plurality of gate electrodes has been proposed by the present inventor (U.S. Ser. No. 757,583 filed on Dec. 27, 1976).
A highly improved memory device is disclosed by the present inventor in his U.S. Ser. No. 878,441 filed on Feb. 16, 1978.
In the above-mentioned memory device, a memory cell is formed substantially perpendicular to the surface of the semiconductor body, and charge carriers are transported mainly by the bulk mobility, thereby raising the packing density and the operation speed, as well as reducing the power dissipation.
However, even in such devices, the operation speed is still subjected to limitation by the following factors, namely, the gate capacitance in the operative state and the space charge storage effect of the minority carriers.
FIG. 20A shows a diagrammatic top view of the conventional memory device and FIGS. 20B and 20C are diagrammatical sections of the memory device shown in FIG. 20A taken along lines 20B-20B' and 20C-20C', respectively.
In the Figures, the memory device comprises a p type substrate 115, an n.sup.+ type source region 113, a p.sup.+ type gate region 114 serving as a word line, an n.sup.- type channel region 112, an n.sup.+ type storage region 111 (an SIT is composed of a source region 113, a gate region 114, a channel region 112, and a drain region 111), a metal electrode 123 (made with aluminum, molybdenum or a low resistivity polycrystalline silicon or the like) which serves as a bit line, and an insulator region 116 formed with a silicon oxide (SiO.sub.2), a silicon nitride (Si.sub.3 N.sub.4) or an aluminum oxide (Al.sub.2 O.sub.3), or with their combination, or the like. The memory array (see FIG. 20A) includes an SIT disposed at each cross point of the word lines and the bit lines. Typical impurity concentrations of the respective semiconductor regions are about: 10.sup.17 to 10.sup.21 cm.sup.-3 for the storage region 111; 10.sup.17 to 10.sup.21 cm.sup.-3 for the source region 113; 10.sup.11 to 10.sup.15 cm.sup.-3 for the channel region 112; 10.sup.17 to 10.sup.21 cm.sup.-3 for the gate region 114; and 10.sup.14 to 10.sup.18 cm.sup.-3 for the substrate 115. The channel width between the gate region 114 is determined by the impurity concentration of the channel region 112 so that the channel region 112 will become pinched off only by the built-in (diffusion) potential established by the pn junction between the gate region 114 and the channel region 112. The storage region 111 forms also a capacitor for storing charge carriers. When charge carriers are stored in the storage region 111, the voltage of this storage region 111 will be raised accordingly to some extent.
Under the conditions stated above, however, the dimensions and the impurity concentrations of those regions forming the SIT must be selected so as to establish a potential barrier in the channel region, so that the charge carriers (electrons in this case) will not be allowed to flow into the storage region 111, from the source region 113 unless an external voltage is applied to the word line and/or bit line.
For example, when the impurity concentration of the n.sup.- type channel region 112 is selected to be 1.times.10.sup.13 cm.sup.-3, 1.times.10.sup.14 cm.sup.-3 or 1.times.10.sup.15 cm.sup.-3, the channel width is selected to be an appropriate value less than 20 .mu.m, 6 .mu.m and 2 .mu.m, respectively. In case the distance between the storage region 111 and the source region 113 is reduced, the transit time of electrons for reading and writing can be reduced also. Therefore, it is desirable that the distance between the storage region 111 and the source region 113 be reduced.
Memory cells which are analogous to that shown in FIGS. 20A to 20C may be represented by the equivalent circuit diagrams shown in FIGS. 20D and 20E. In FIG. 20D, the circuit comprises an SIT 100, a capacitor 101, a bit line 123 and a word line 124, wherein charge carriers are stored in the capacitor 101 and are transported into the bit line 123 under the control of the gate region connected to the word line 124. On the other hand, a floating gate region is employed in FIG. 20E, wherein stored charge carriers in the capacitor 101 are transported into the bit line 123 by changing the voltage applied to the word line 124 relative to the bit line 123.
The operational behavior of the conventional memory device will become clear by the following description.
When it is desired to write data into a memory cell of FIGS. 20A to 20C, a positive voltage is applied to the word line (gate region) 114 to decrease the height of the potential barrier produced in the channel region 112, while at the same time a predetermined positive voltage is given to the bit line 123. In this case, since the height of the potential barrier established in the channel region 112 is decreased, electrons are allowed to flow into the source region 113 from the storage region 111. As electrons flow from the storage region 111, the voltage of the storage region 111 becomes higher in the positive polarity due to the lack of electrons having a negative charge. When the voltage of the bit line (for writing) 123 becomes equal to the voltage of the storage region 11, electrons will cease to flow. In case the voltage applied for writing data is removed, then the potential barrier reappears in the channel region 112, and accordingly the storage region 111 is held charged with a positive voltage. When it is desired to read data (to retrieve data), a predetermined negative voltage is applied to the bit line 123, while at the same time a forward voltage (positive voltage in this case) is given to the word line (gate region) 114. Whereupon, electrons are allowed to flow into the storage region 111 from the source region 113. By the appearance of this current, it can be determined as to whether or not the memory cell is in the state of either "1" or "0".
In the above-stated memory devices, the gate region 114 is formed to completely surround the channel region 112. Thus, if the gate region 114 is used to serve as a word line, the capacitance of the word line 114 is not sufficiently small for achieving a high-speed reading and writing operation.
FIGS. 21A and 21B are diagrammatic sectional views of another semiconductor memory device. This memory device comprises an n.sup.+ type source region 113 to serve as a bit line for reading, an n.sup.- type channel region 112, an n.sup.+ type storage region 111, a p.sup.+ type gate region 114 to serve as a word line, a metal electrode 121 to serve as a bit line for writing, and an insulator region 116 forming a metal-insulator-semiconductor (MIS) structure. The memory storage region 111 is disposed in the surface of the semiconductor body. This region 111 may also be disposed in an inner region located apart from the surface.
When it is desired to transport electrons into the storage region 111, a positive voltage is applied to the word line 114, while a positive voltage is given to the bit line (for writing) 121. Then, electrons will flow into the storage region through the channel region 112, from the source region 113.
When it is desired to keep the electrons stored in the storage region 111, the voltage given to the bit line (for writing) 121 may be lowered to about one half of the voltage for transporting electrons into the storage region 111.
When it is desired to read data or retrieve electrons from the storage region 111, the voltage of the bit line (for writing) 121 is re-set, to for example the ground potential, while a positive voltage is given to the word line 114. Then, electrons which have been stored in the storage region 111 become able to flow into the source region 113 (serving as a bit line for reading) through the channel region 112, and thus the presence of electrons stored in the storage region 111 can be detected. Also, the shortage of charge carriers may be utilized to represent the state of storage.
In FIGS. 21A and 21B mentioned above, the gate region 114 is provided so as to surround the channel region 112, and therefore in case the gate region 114 is utilized as a word line, the capacitance of the gate region will not be negligible in the operative state. However, it is preferable to minimize the gate capacitance as small as possible for attaining a higher operation speed.
In the above-mentioned device, a punch-through current should not be allowed to flow between the gate region 114 and the substrate 115, and the charges which are stored in the storage region 111 must be preserved for an extended period of time. Therefore, an excessively high voltage cannot be applied between the respective regions. A punch-through current should be carefully avoided in such structure where the storage capacitance is formed between the storage region 111 and the substrate 115, and also where the storage capacitance is formed by the capacitance of a MOS (metal-oxide-semiconductor) disposed in the vicinity of the surface of the semiconductor body.